FPGA development kit arrived

This post is applicable for the USB Scanner design

Recently arrived: SPARTAN III start kit. This enables to start experimenting with the SPARTAN FPGA and multiple clock domains. The problem with the CPLD was that it couldn't handle multiple clock sources which where a-synchronous to eachother. The SPARTANII/III FPGA's contain dual port ram and are excellent for creating clock adaptation FIFO's ....

Successfully got the board up and running, succeeded to compile VHDL and programm the on board PROM and reconfigure the FPGA in circuit using JTAG.

[Lab Hardware]